標(biāo)準(zhǔn)號：BS IEC 60748-2-12-2001
中文標(biāo)準(zhǔn)名稱：半導(dǎo)體器件.集成電路.數(shù)字集成電路.可編程序邏輯設(shè)備的空白詳細(xì)規(guī)范
英文標(biāo)準(zhǔn)名稱：Semiconductor devices - Integrated circuits - Digital integrated circuits - Blank detail specification for programmable logic devices (PLDs)
標(biāo)準(zhǔn)類型：L56
發(fā)布日期：2001/6/15 12:00:00
實施日期：2001/6/15 12:00:00
中國標(biāo)準(zhǔn)分類號：L56
國際標(biāo)準(zhǔn)分類號：31.200
適用范圍：Semiconductor devices —Integrated circuits — Part 2-12: Digital integrated circuits —Blank detail specification for programmable logic devices (PLDs) FOREWORD INTRODUCTION Clause 1 Marking and ordering information 1.1 Marking 1.2 Ordering information 2 Application related description 3 Specification of the function 3.1 Block diagram 3.2 Identification and function of terminals 3.3 Functional description 3.4 Family-related characteristics 4 Limiting values (absolute maximum rating system) 5 Operating conditions (within the specified operating temperature range), 6 Electrical characteristics 6.1 Static characteristics 6.2 Dynamic characteristics 6.3 Timing diagram 6.4 Capacitances 7 Programming 7.1 Programming mode 7.2 Erasing mode (if applicable) 7.3 Number of programming-erasing cycles (where appropriate) 7.4 Data retention information 8 Additional information 9 Screening (if required) 10 Quality assessment procedures 10.1 Qualification approval procedures 10.2 Capability approval procedures 11 Structural similarity procedures 12 Test conditions and inspection requirements 12.1 General 12.2 Sampling requirements and formation of inspection lots, 12.3 Inspection tables 12.4 Delayed deliveries 13 Additional measurement method 13.1 Data retention test (destructive test) 13.2 Write/erase endurance: number of programming cycles (destructive test) 13.3 Programmability Reference documents Table 1 - Group A: Lot-by-lot Table 2 - Group B: Lot-by-lot Table 3 - Group C: Periodic Table 4 - Group D